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EM78P159N
8-Bit Microcontroller with OTP ROM
Product Specification
DOC. VERSION 1.0
ELAN MICROELECTRONICS CORP.
March 2006
Trademark Acknowledgments: IBM is a registered trademark and PS/2 is a trademark of IBM. Windows is a trademark of Microsoft Corporation. ELAN and ELAN logo are trademarks of ELAN Microelectronics Corporation.
Copyright (c) 2006 by ELAN Microelectronics Corporation
All Rights Reserved
Printed in Taiwan
The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes no responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics makes no commitment to update, or to keep current the information and material contained in this specification. Such information and material may change to conform to each confirmed order. In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors, omissions, or other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not be liable for direct, indirect, special incidental, or consequential damages arising from the use of such information or material. The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and may be used or copied only in accordance with the terms of such agreement. ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of ELAN Microelectronics product in such applications is not supported and is prohibited. NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY ANY MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS.
ELAN MICROELECTRONICS CORPORATION
Headquarters: No. 12, Innovation Road 1 Hsinchu Science Park Hsinchu, Taiwan 30077 Tel: +886 3 563-9977 Fax: +886 3 563-9966 http://www.emc.com.tw Hong Kong: Elan (HK) Microelectronics Corporation, Ltd. Rm. 1005B, 10/F Empire Centre 68 Mody Road, Tsimshatsui Kowloon , HONG KONG Tel: +852 2723-3376 Fax: +852 2723-7780 elanhk@emc.com.hk Shenzhen: Elan Microelectronics Shenzhen, Ltd. SSMEC Bldg., 3F, Gaoxin S. Ave. Shenzhen Hi-Tech Industrial Park Shenzhen, Guandong, CHINA Tel: +86 755 2601-0565 Fax: +86 755 2601-0500 USA : Elan Information Technology Group (USA) 1821 Saratoga Ave., Suite 250 Saratoga, CA 95070 USA Tel : +1 408 366-8225 Fax: +1 408 366-8220
Europe : Elan Microelectronics Corp. (Europe) Siewerdtstrasse 105 8050 Zurich, SWITZERLAND Tel: +41 43 299-4060 Fax: +41 43 299-4079 http://www.elan-europe.com
Shanghai: Elan Microelectronics Shanghai, Ltd. 23/Bldg. #115 Lane 572, Bibo Road Zhangjiang Hi-Tech Park Shanghai, CHINA Tel: +86 21 5080-3866 Fax: +86 21 5080-4600
Contents
Contents
1 2 3 General Description .................................................................................................. 1 1.1 Comparison between EM78P159N, EM78P154N, and EM78P157N ................ 1 Features ..................................................................................................................... 1 Pin Assignments and Descriptions ......................................................................... 3 3.1 3-2 3.3 4 4.1 EM78P159NP and EM78P159NM Pin Description ............................................ 4 EM78P159NAS Pin Description ......................................................................... 4 EM78P159NKM Pin Description ........................................................................ 5 Operational Registers......................................................................................... 6
4.1.1 4.1.2 4.1.3 4.1.4 4.1.5 4.1.6 4.1.7 4.1.8 4.1.9 4.1.10 R0 (Indirect Addressing Register) .......................................................................6 R1 (Time Clock /Counter)....................................................................................6 R2 (Program Counter) & Stack ...........................................................................7 R3 (Status Register) ............................................................................................8 R4 (RAM Select Register)...................................................................................9 R5 ~ R6 (Port 5 ~ Port 6) ....................................................................................9 RD (Manual Calibration Register) .......................................................................9 RE (Wake Up Control Register) ........................................................................10 RF (Interrupt Status Register) ...........................................................................10 R10 ~ R3F .........................................................................................................10 A (Accumulator).................................................................................................11 CONT (Control Register)...................................................................................11 IOC5 ~ IOC6 (I/O Port Control Register) ..........................................................12 IOCA (Prescaler Counter Register)...................................................................12 IOCB (Pull-Down Control Register)...................................................................12 IOCC (Open-Drain Control Register) ................................................................13 IOCD (Pull-High Control Register) ....................................................................13 IOCE (WDT Control Register) ...........................................................................14 IOCF (Interrupt Mask Register).........................................................................15
Function Description ................................................................................................ 6
4.2
Special Purpose Registers ............................................................................... 11
4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 4.2.7 4.2.8 4.2.9
4.3 4.4 4.5
TCC/WDT & Prescaler ..................................................................................... 15 I/O Ports ........................................................................................................... 16
4.4.1 4.5.1 4.5.2 4.5.3 Usage of Port 6 Input Change Wake-up/Interrupt Function..............................18 RESET ..............................................................................................................19 The Summary of the Initialized Values for Registers ........................................22 The Status of RST, T, and P of STATUS Register .............................................24
RESET and Wake-up ....................................................................................... 19
4.6
Interrupt ............................................................................................................ 25
Product Specification (V1.0) 03.10.2006
* iii
Contents
4.7
Oscillator .......................................................................................................... 26
4.7.1 4.7.2 4.7.3 4.7.4 Oscillator Modes................................................................................................26 Crystal Oscillator/Ceramic Resonators (XTAL) .................................................27 External RC Oscillator Mode.............................................................................28 Internal RC Oscillator Mode ..............................................................................29 Code Option Register (Word 0).........................................................................30 Customer ID Register (Word 1).........................................................................31 Customer ID Register (Word 2).........................................................................32
4.8
CODE Option Register ..................................................................................... 30
4.8.1 4.8.2 4.8.3
4.9
Power On Considerations ................................................................................ 32
4.10 External Power On Reset Circuit..................................................................... 32 4.11 Residue-Voltage Protection............................................................................. 33 4.12 Instruction Set ................................................................................................. 34 4.13 Timing Diagrams ............................................................................................. 37 5 6 Absolute Maximunm Ratings ................................................................................. 38 Electrical Characteristics ....................................................................................... 38 6.1 6.2 DC Electrical Characteristic.............................................................................. 38 AC Electrical Characteristic.............................................................................. 39
APPENDIX
A B C Package Types......................................................................................................... 40 Package Information............................................................................................... 40 Quality Assurance and Reliability ......................................................................... 42 C.1 Reliability Test .................................................................................................. 42 C.2 Power-On Reset and Vdd Voltage Drop/Rise Timing Test ............................... 43 C.3 Address Trap Detect......................................................................................... 43
Specification Revision History
Doc. Version 1.0 Revision Description Initial Release Version Date 2006/03/10
iv *
Product Specification (V1.0) 03.10.2006
EM78P159N 8-Bit Microcontroller with OTP ROM
1
General Description
EM78P159N is an 8-bit microprocessor designed and developed with low-power, high-speed CMOS technology. It is equipped with 1K*13-bits Electrical One Time Programmable Read Only Memory (OTP-ROM). It provides three PROTECTION bits to prevent user's code in the OTP memory from being intruded. 8 OPTION bits are also available to meet user's requirements. With its OTP-ROM feature, the EM78P159N is able to offer a convenient way of developing and verifying user's programs. Moreover, user can take advantage of ELAN Writer to easily program his development code.
1.1
Comparison between EM78P159N, EM78P154N, and EM78P157N
To find out what similarities and differences are between EM78P159N EM78P154N and EM78P157N, click the following link. AN-001 EM78P154N/159N introduction and comparison with EM78P157N
2
Features
Operating voltage range:
* 2.1V~5.5V at 0C~70C * 2.3V~5.5V at 40C~85C
Operating frequency range (base on 2 clocks ):
* Crystal mode: DC~20MHz at 5.0V, DC~8MHz at 3.0V, DC~4MHz at 2.1V * ERC mode: DC~4MHz at 5.0~2.1V * IRC mode: 4 choices of frequencies available; i.e., 8M, 4M, 1M, & 455kHz
IRC mode:
* All these four main frequencies can be trimmed by programming with four
calibrated bits in the ICE159N Simulator. OTP is auto trimmed by DWTR.
* Temperature, Voltage, and Process changes will influence the frequency drift * Frequency deviation is only 4.5% after auto trimming (based on Vdd=5V,
Ta=25C) Fast set-up time only requires about 2ms in high XTAL and 32CLKS in IRC mode from wake up to operating mode
Product Specification (V1.0) 03.10.2006
(This specification is subject to change without further notice)
*1
EM78P159N 8-Bit Microcontrollerwith OTP ROM
Low power consumption:
* Less then 2mA at 5V/4MHz * Typically 20A at 3V/32kHz * Typically 1A during Sleep mode
1K x 13 bits on chip ROM One security register to prevent intrusion of OTP memory codes One configuration register to accommodate user's requirements 48x 8 bits on chip registers (SRAM, general purpose register) 2 bi-directional I/O ports 5 level stacks for subroutine nesting 8-bit real time clock/counter (TCC) with selective signal sources, trigger edges, and overflow interrupt Two clocks per instruction cycle Power down (SLEEP) mode Three available interruptions:
* TCC overflow interrupt * Input-port status changed interrupt (wake up from Sleep mode) * External interrupt
Programmable free running watchdog timer 8 programmable pull-high pins 8 programmable pull-down pins 8 programmable open-drain pins 2 programmable R-option pins Package types:
* * * *
18 pin DIP 300mil 18 pin SOP 300mil
: EM78P159NP : EM78P159NM
20 pin SSOP 209mil : EM78P159NAS 20 pin SSOP 209mil : EM78P159NKM
99.9% single instruction cycle commands The transient point of system frequency between HXT and LXT is around 400kHz
2*
Product Specification (V1.0) 03.10.2006
(This specification is subject to change without further notice)
EM78P159N 8-Bit Microcontroller with OTP ROM
3
Pin Assignments and Descriptions
P52 P53 P54/TCC /RESET Vss P60/INT P61 P62 P63 1 2 3 4 5 6 7 8 9 EM78P159NP EM78P159NM 18 17 16 15 14 13 12 11 10 P51 P50 P56/OSCI P55/OSCO VDD P67 P66 P65 P64
Figure3-1a EM78P159NP/M Pin Assignments
NC P52 P53 P54/TCC /RESET Vss P60/INT P61 P62 P63
1 2 3 EM78P159NAS 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
NC P51 P50 P56/OSCI P55/OSCO VDD P67 P66 P65 P64
P52 P53 P54/TCC /RESET Vss Vss P60/INT P61 P62 P63
1 2 3 4 5 6 7 8 9 10 EM78P159NKM
20 19 18 17 16 15 14 13 12 11
P51 P50 P56/OSCI P55/OSCO VDD VDD P67 P66 P65 P64
Figure3-1b EM78P159NAS Pin Assignments
Figure3-1c EM78P159NKM Pin Assignments
Product Specification (V1.0) 03.10.2006
(This specification is subject to change without further notice)
*3
EM78P159N 8-Bit Microcontrollerwith OTP ROM
3.1
Symbol VDD P56/OSCI
EM78P159NP and EM78P159NM Pin Description
Pin No. 14 16 Type I/O Power supply General-purpose I/O pin XTAL type: Crystal input terminal or external clock input pin ERC type: RC oscillator input pin General-purpose I/O pin XTAL type: Output terminal for crystal oscillator or external clock input pin RC type: Instruction clock output External clock signal input General-purpose I/O pin The real time clock/counter (with Schmitt trigger input pin), must be tied to VDD or VSS if not in use. Input pin with Schmitt trigger. If this pin remains at logic low, the controller will also remain in reset condition. P50 ~ P53 are bi-directional I/O pins. P50 and P51 can also be defined as the R-option pins P50 ~ P53 can be pulled-down by software P60 ~ P67 are bi-directional I/O pins. These can be pulled-high or can be open-drain by software programming P60 ~ P63 can also be pulled-down by software Function
P55/OSCO
15
I/O
P54/TCC /RESET P50 ~ P53
3 4 17, 18, 1, 2 6 ~ 13 6 5
I/O I I/O
P60 ~ P67 /INT VSS
I/O I -
External interrupt pin triggered by falling edge Ground
3-2
Symbol VDD P56/OSCI
EM78P159NAS Pin Description
Pin No. 15 17 Type I/O Power supply. General-purpose I/O pin XTAL type: Crystal input terminal or external clock input pin ERC type: RC oscillator input pin General-purpose I/O pin XTAL type: Output terminal for crystal oscillator or external clock input pin RC type: Instruction clock output External clock signal input General-purpose I/O pin The real time clock/counter (with Schmitt trigger input pin), must be tied to VDD or VSS if not in use. Input pin with Schmitt trigger. If this pin remains at logic low, the controller will also remain in reset condition. P50 ~ P53 are bi-directional I/O pins P50 and P51 can also be defined as the R-option pins P50 ~ P53 can be pulled-down by software P60 ~ P67 are bi-directional I/O pins. These can be pulled-high or can be open-drain by software programming P60 ~ P63 can also be pulled-down by software Function
P55/OSCO
16
I/O
P54/TCC /RESET P50~P53
4 5 18, 19, 2, 3 7~14 7 6
I/O I I/O
P60~P67 /INT VSS
I/O I -
External interrupt pin triggered by falling edge Ground
4*
Product Specification (V1.0) 03.10.2006
(This specification is subject to change without further notice)
EM78P159N 8-Bit Microcontroller with OTP ROM
3.3
Symbol VDD P56/OSCI
EM78P159NKM Pin Description
Pin No. 15,16 18 Type I/O Power supply. General-purpose I/O pin XTAL type: Crystal input terminal or external clock input pin. ERC type: RC oscillator input pin. General-purpose I/O pin XTAL type: Output terminal for crystal oscillator or external clock input pin RC type: Instruction clock output External clock signal input General-purpose I/O pin The real time clock/counter (with Schmitt trigger input pin), must be tied to VDD or VSS if not in use. Input pin with Schmitt trigger. If this pin remains at logic low, the controller will also remain in reset condition. P50 ~ P53 are bi-directional I/O pins. P50 and P51 can also be defined as the R-option pins. P50 ~ P53 can be pulled-down by software. P60 ~ P67 are bi-directional I/O pins. These can be pulled-high or can be open-drain by software programming. P60 ~ P63 can also be pulled-down by software Function
P55/OSCO
17
I/O
P54/TCC /RESET P50~P53
3 4 19, 20, 1, 2 7~14 7 5, 6
I/O I I/O
P60~P67 /INT VSS
I/O I -
External interrupt pin triggered by falling edge Ground
Product Specification (V1.0) 03.10.2006
(This specification is subject to change without further notice)
*5
EM78P159N 8-Bit Microcontrollerwith OTP ROM
4
Function Description
OSCO /RESET OSCI
WDT timer Oscillator/Timing
Control
TCC
/INT
Prescaler IOCA
ROM
R2
Stack
RAM
Interrupt Controller
Instruction Register
R3
ALU
R4
R1(TCC)
Instruction Decoder
ACC
DATA & CONTROL BUS
P60//INT P61 P62 P63 P64 P65 P66 P67 P50 P51 P52 P53 P54 P55 P56
IOC6 R6
I/O PORT 6
IOC5 R5
I/O PORT 5
Figure 4-1 Function Block Diagram
4.1
Operational Registers
4.1.1 R0 (Indirect Addressing Register)
R0 is not a physically implemented register. Its major function is to perform as an indirect addressing pointer. Any instruction using R0 as a pointer actually accesses data pointed by the RAM Select Register (R4).
4.1.2 R1 (Time Clock /Counter)
Increased by an external signal edge, which is defined by TE bit (CONT-4) through the TCC pin, or by the instruction cycle clock. Writable and readable as any other registers. Defined by resetting PAB(CONT-3). The prescaler is assigned to TCC, if the PAB bit (CONT-3) is reset. The contents of the prescaler counter will be cleared only when TCC register is written with a value.
6*
Product Specification (V1.0) 03.10.2006
(This specification is subject to change without further notice)
EM78P159N 8-Bit Microcontroller with OTP ROM
4.1.3 R2 (Program Counter) & Stack
Depending on the device type, R2 and hardware stack are 10-bit wide. The structure is depicted in the following figure.
PC (A9 ~ A0)
Reset Vector Interrupt Vector
000H 008H
User Memory Space
Stack Level 1 Stack Level 2 Stack Level 3 Stack Level 4 Stack Level 5
On-chip Program Memory
3FFH
Figure 4-2 Program Counter Organization
Generating 1024x13 bits on-chip OTP ROM addresses to the relative programming instruction codes. One program page is 1024 words long. R2 is set as all "0" when under RESET condition. "JMP" instruction allows direct loading of the lower 10 program counter bits. Thus, "JMP" allows PC to go to any location within a page. "CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed into the stack. Thus, the subroutine entry address can be located anywhere within a page. "RET" ("RETLk", "RETI") instruction loads the program counter with the contents of the top-level stack. "ADD R2, A" allows a relative address to be added to the current PC, and the ninth and succeeding bits of the PC will increase progressively. "MOV R2, A" allows loading of an address from the "A" register to the lower 8 bits of the PC, and the ninth and tenth bits (A8 ~ A9) of the PC will remain unchanged. Any instruction (except "ADD R2,A") that is written to R2 (e.g., "MOV R2, A", "BC R2, 6",) will cause the ninth bit and the tenth bit (A8 ~ A9) of the PC to remain unchanged. All instructions are single instruction cycle (fclk/2 or fclk/4) except for the instruction that would change the contents of R2. Such instruction will need one more instruction cycle.
Product Specification (V1.0) 03.10.2006
(This specification is subject to change without further notice)
*7
EM78P159N 8-Bit Microcontrollerwith OTP ROM
The Data Memory Configuration is as follows:
Address 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 3F R0 R1 R2 R3 R4 R5 R6 Reserve Reserve Reserve Reserve Reserve Reserve RD RE RF R PAGE Registers (IAR) (TCC) (PC) (Status) (RSR) (Port5) (Port6) Reserve CONT Reserve Reserve Reserve IOC5 IOC6 Reserve Reserve Reserve IOCA IOCB IOCC IOCD IOCE IOCF IOC PAGE Registers (Control Register)
(I/O Port Control Register) (I/O Port Control Register)
(Only for simulator) (Wake up control) (Interrupt Status) General Registers
(Prescaler Control Register) (Pull-down Register) (Open-drain Control) (Pull-high Control Register) (WDT Control Register) (Interrupt Mask Register)
4.1.4 R3 (Status Register)
Bit 7 GP2 Bit 6 GP1 Bit 5 GP0 Bit 4 T Bit 3 P Bit 2 Z Bit 1 DC Bit 0 C
Bit 0 (C) Bit 1 (DC) Bit 2 (Z)
Carry flag Auxiliary carry flag Zero flag. Set to "1" if the result of an arithmetic or logic operation is zero.
Bit 3 (P)
Power down bit. Set to "1" during power on or by a "WDTC" command; and reset to "0" by a "SLEP" command.
Bit 4 (T)
Time-out bit. Set to "1" with the "SLEP" and "WDTC" commands, or during power up; and reset to "0" by WDT time-out.
Bit 5 ~7 (GP0 ~ 2) General-purpose read/write bits.
8*
Product Specification (V1.0) 03.10.2006
(This specification is subject to change without further notice)
EM78P159N 8-Bit Microcontroller with OTP ROM
4.1.5 R4 (RAM Select Register)
Bits 0~5 Bits 6~7 are used to select registers (Address: 00~06, 0F~3F) in the indirect addressing mode. Not used (read only). Set these bits to "1" all the time.
The "Z" flag of R3 will set to "1" when the R4 content is equal to "3F." When R4=R4+1, the R4 content will select "R0."
4.1.6 R5 ~ R6 (Port 5 ~ Port 6)
R5 and R6 are I/O registers. Only the lower 7 bits of R5 are available.
4.1.7 RD (Manual Calibration Register)
Bit 7 EM78P159N ICE159N Simulator X Bit 6 X Bit 5 X Bit 4 X Bit 3 X C3 Bit 2 X C2 Bit 1 X C1 Bit 0 X C0
In EM78P159N: The register does not exist in real chip. In ICE159N Simulator: C3 ~ C0 are IRC calibration bits in MCIRC mode. Bit 3 ~ Bit 0 (C3 ~ C0): are the Calibrators of internal RC mode
C3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 C2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 C1 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 C0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 Cycle Time (ns) 390.6 365.0 342.5 322.6 304.9 289.0 274.7 261.8 250.0 239.2 229.4 220.3 211.9 204.1 196.7 190.1 Frequency (MHz) 2.56 2.74 2.92 3.1 3.28 3.46 3.64 3.82 4.00 4.18 4.36 4.54 4.72 4.9 5.08 5.26
NOTES: 1. Frequency values shown are theoretical and taken from an instance of a high frequency mode. Hence they are shown for reference only. Definite values will depend on the actual process. 2. Similar way of calculation is also applicable to Low Frequency mode.
Bits 4~7: Not used
Product Specification (V1.0) 03.10.2006
(This specification is subject to change without further notice)
*9
EM78P159N 8-Bit Microcontrollerwith OTP ROM
4.1.8 RE (Wake Up Control Register)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 ICWE Bit 0 -
Bits 0:
Not used.
Bit 1 (ICWE): Port 6 input status change wake-up enable bit 0 = Disable Port 6 input status change wake-up 1 = Enable Port 6 input status change wake-up Bits 2 ~ 7: Not used.
4.1.9
Bit 7 -
RF (Interrupt Status Register)
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 EXIF Bit 1 ICIF Bit 0 TCIF
"1" means interrupt request, and "0" means no interrupt occurs. Bit 0 (TCIF): TCC overflow interrupt flag. Set when TCC overflows. Reset by software. Bit 1 (ICIF): Port 6 input status change interrupt flag. Set when Port 6 input changes. Reset by software. Bit 2 (EXIF): External interrupt flag. Set by falling edge on /INT pin. Reset by software. Bits 3 ~ 7: Not used.
RF can be cleared by instruction but cannot be set. IOCF is the interrupt mask register.
NOTE The result of reading RF is the "logic AND" of RF and IOCF.
4.1.10 R10 ~ R3F
These are all 8-bit general-purpose registers.
10 *
Product Specification (V1.0) 03.10.2006
(This specification is subject to change without further notice)
EM78P159N 8-Bit Microcontroller with OTP ROM
4.2 Special Purpose Registers
4.2.1 A (Accumulator)
Internal data transfer, or instruction operand holding It cannot be addressed.
4.2.2 CONT (Control Register)
Bit 7 Bit 6 /INT Bit 5 TS Bit 4 TE Bit 3 PSRE Bit 2 PSR2 Bit 1 PSR1 Bit 0 PSR0
Bit 0 (PSR0) ~ Bit 2 (PSR2): TCC prescaler bits
PSR2 0 0 0 0 1 1 1 1 PSR1 0 0 1 1 0 0 1 1 PSR0 0 1 0 1 0 1 0 1 TCC Rate 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256
Bit 3 (PSRE): Prescaler enable bit for TCC. 0 = prescaler disabled bit, TCC rate is 1:1 1 = prescaler enabled bit, TCC rate is set as Bit2~Bit0 Bit 4 (TE): TCC signal edge 0 = increment if the transition from low to high takes place on TCC pin 1 = increment if the transition from high to low takes place on TCC pin Bit 5 (TS): TCC signal source 0 = internal instruction cycle clock, P54 is a bi-directional I/O PIN 1 = transition on TCC pin Bit 6 (/INT): Interrupt enable flag 0 = masked by DISI or hardware interrupt 1 = enabled by ENI/RETI instructions Bit 7: Not used.
CONT register is both readable and writable.
Product Specification (V1.0) 03.10.2006
(This specification is subject to change without further notice)
* 11
EM78P159N 8-Bit Microcontrollerwith OTP ROM
4.2.3 IOC5 ~ IOC6 (I/O Port Control Register)
"1" put the relative I/O pin into high impedance, while "0" defines the relative I/O pin as output. Only the lower 7 bits of IOC5 can be defined. IOC5 and IOC6 registers are both readable and writable.
4.2.4 IOCA (Prescaler Counter Register)
IOCA register is readable. The value of IOCA is equal to the contents of Prescaler counter. Down counter
4.2.5 IOCB (Pull-Down Control Register)
Bit 7 /PD7 Bit 6 /PD6 Bit 5 /PD5 Bit 4 /PD4 Bit 3 /PD3 Bit 2 /PD2 Bit 1 /PD1 Bit 0 /PD0
Bit 0 (/PD0): Control bit is used to enable the pull-down of P50 pin. 0 = Enable internal pull-down 1 = Disable internal pull-down Bit 1 (/PD1): Control bit is used to enable the pull-down of P51 pin. Bit 2 (/PD2): Control bit is used to enable the pull-down of P52 pin. Bit 3 (/PD3): Control bit is used to enable the pull-down of P53 pin. Bit 4 (/PD4): Control bit is used to enable the pull-down of P60 pin. Bit 5 (/PD5): Control bit is used to enable the pull-down of P61 pin. Bit 6 (/PD6): Control bit is used to enable the pull-down of P62 pin. Bit 7 (/PD7): Control bit is used to enable the pull-down of P63 pin. IOCB Register is both readable and writable.
12 *
Product Specification (V1.0) 03.10.2006
(This specification is subject to change without further notice)
EM78P159N 8-Bit Microcontroller with OTP ROM
4.2.6 IOCC (Open-Drain Control Register)
Bit 7 OD7 Bit 6 OD6 Bit 5 OD5 Bit 4 OD4 Bit 3 OD3 Bit 2 OD2 Bit 1 OD1 Bit 0 OD0
Bit 0 (OD0): Control bit is used to enable the open-drain of P60 pin. 0 = Disable open-drain output 1 = Enable open-drain output Bit 1 (OD1): Control bit is used to enable the open-drain of P61 pin. Bit 2 (OD2): Control bit is used to enable the open-drain of P62 pin. Bit 3 (OD3): Control bit is used to enable the open-drain of P63 pin. Bit 4 (OD4): Control bit is used to enable the open-drain of P64 pin. Bit 5 (OD5): Control bit is used to enable the open-drain of P65 pin. Bit 6 (OD6): Control bit is used to enable the open-drain of P66 pin. Bit 7 (OD7): Control bit is used to enable the open-drain of P67 pin. IOCC Register is both readable and writable.
4.2.7 IOCD (Pull-High Control Register)
Bit 7 /PH7 Bit 6 /PH6 Bit 5 /PH5 Bit 4 /PH4 Bit 3 /PH3 Bit 2 /PH2 Bit 1 /PH1 Bit 0 /PH0
Bit 0 (/PH0): Control bit is used to enable the pull-high of P60 pin. 0 = Enable internal pull-high 1 = Disable internal pull-high Bit 1 (/PH1): Control bit is used to enable the pull-high of P61 pin. Bit 2 (/PH2): Control bit is used to enable the pull-high of P62 pin. Bit 3 (/PH3): Control bit is used to enable the pull-high of P63 pin. Bit 4 (/PH4): Control bit is used to enable the pull-high of P64 pin. Bit 5 (/PH5): Control bit is used to enable the pull-high of P65 pin. Bit 6 (/PH6): Control bit is used to enable the pull-high of P66 pin. Bit 7 (/PH7): Control bit is used to enable the pull-high of P67 pin. IOCD Register is both readable and writable.
Product Specification (V1.0) 03.10.2006
(This specification is subject to change without further notice)
* 13
EM78P159N 8-Bit Microcontrollerwith OTP ROM
4.2.8 IOCE (WDT Control Register)
Bit 7 WDTE Bit 6 EIS Bit 5 Bit 4 ROC Bit 3 PSWE Bit 2 PSW2 Bit 1 PSW1 Bit 0 PSW0
Bit 7 (WDTE): Control bit used to enable the Watchdog timer. 0 = Disable WDT 1 = Enable WDT WDTE is both readable and writable. Bit 6 (EIS): Control bit is used to define the function of P60 (/INT) pin. 0 = P60, bi-directional I/O pin. 1 = /INT, external interrupt pin. In this case, the I/O control bit of P60 (Bit 0 of IOC6) must be set to "1." When EIS is "0," the path of /INT is masked. When EIS is "1," the status of /INT pin can also be read by way of reading Port 6 (R6). See Figure 4-4a under Section 4.4 for reference. EIS is both readable and writable. Bit 5: Not used
Bit 4 (ROC): ROC is used for the R-option. Setting the ROC to "1" will enable the status of R-option pins (P50P51) that are read by the controller. Clearing the ROC will disable the R-option function. If the R-option function is selected, you must connect the P51 pin or/and P50 pin to VSS with a 430K external resistor (Rex). If the Rex is connected/disconnected, the status of P50 (P51) is read as "0" / "1." Refer to Figure 4-5 under Section 4.4 for reference. Bit 3 (PSWE): Prescaler enable bit for WDT 0 = prescaler disable bit, WDT rate is 1:1. 1 = prescaler enable bit, WDT rate is set as Bit4~Bit2. Bit 2 (PSW2) ~ Bit 0 (PSW0): WDT prescaler bits
PSW2 0 0 0 0 1 1 1 1 PSW1 0 0 1 1 0 0 1 1 PSW0 0 1 0 1 0 1 0 1 WDT Rate 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256
14 *
Product Specification (V1.0) 03.10.2006
(This specification is subject to change without further notice)
EM78P159N 8-Bit Microcontroller with OTP ROM
4.2.9 IOCF (Interrupt Mask Register)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 EXIE Bit 1 ICIE Bit 0 TCIE
Bit 0 (TCIE): TCIF interrupt enable bit 0 = disable TCIF interrupt 1 = enable TCIF interrupt Bit 1 (ICIE): ICIF interrupt enable bit 0 = disable ICIF interrupt 1 = enable ICIF interrupt Bit 2 (EXIE): EXIF interrupt enable bit 0 = disable EXIF interrupt 1 = enable EXIF interrupt Bits 3~7: Not used
Individual interrupt is enabled by setting its associated control bit in the IOCF to "1." Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction. Refer to Figure 4-7 in Section 4.6 for further reference. IOCF register is both readable and writable.
4.3 TCC/WDT & Prescaler
There are two 8-bit counters available as prescalers for the TCC and WDT respectively. The PSR0 ~ PSR2 bits of the CONT register are used to determine the ratio of the prescaler of TCC, and the PWR0 ~ PWR2 bits of the IOCE register are used to determine the prescaler of WDT. The prescaler (PSR0 ~ PSR2) will be cleared by the instruction each time it writes to TCC. The WDT and prescaler will be cleared by the "WDTC" and "SLEP" instructions. R1 (TCC) is an 8-bit timer/counter. The clock source of TCC can be internal or external clock input (edge selectable from TCC pin). If TCC signal is sourced from internal clock, TCC will increase by 1 at every instruction cycle (without prescaler). CLK=Fosc/2 or CLK=Fosc/4 application is determined by the CODE Option bit CLK status. CLK=Fosc/2 is used if CLK bit is "0," and CLK=Fosc/4 is used if CLK bit is "1." If TCC signal source comes from external clock input, TCC is increased by 1 at every falling edge or rising edge of TCC pin. The watchdog timer is a free running on-chip RC oscillator. The WDT will keep on running even when the oscillator driver has been turned off (i.e., in Sleep mode). During normal operation or Sleep mode, a WDT time-out (if enabled) will cause the device to reset. The WDT can be enabled or disabled any time during Normal mode by software programming. Refer to WDTE bit of IOCE register in Section 4.2.8. Without prescaler, the WDT time-out period is approximately 18 ms1 (default).
1
Vdd = 5V, set up time period = 16.8ms 30% Vdd = 3V, set up time period = 18ms 30% Product Specification (V1.0) 03.10.2006
(This specification is subject to change without further notice)
* 15
EM78P159N 8-Bit Microcontrollerwith OTP ROM
4.4 I/O Ports
The I/O registers, both Port 5 and Port 6, are bi-directional tri-state I/O ports. Port 6 can be pulled high internally by software. In addition, Port 6 can also features an open-drain output through software and an Input status change interrupt (or wake-up) function. P50 ~ P53 and P60 ~ P63 pins can be pulled down by software. Each I/O pin can be defined as "input" or "output" pin by the I/O control register (IOC5 ~ IOC6). P50~P51 are the R-option pins enabled by setting the ROC bit in the IOCE register to "1." When the R-option function is used, it is recommended that P50 ~ P51 are used as output pins. When R-option is in enable state, P50 ~ P51 must be programmed as input pins. Under R-option mode, the current/power consumption by Rex should be taken into the consideration to promote energy conservation. The I/O registers and I/O control registers are both readable and writable. The I/O interface circuits for Port 5 and Port 6 are shown in the following figures (Figures 4-3, 4-4a, 4-4b, & 4-5).
PCRD
Q _ Q
P R C L
D CLK PC W R
PORT
Q _ Q
P R C L
D CLK PD W R
IO D
PDRD 0 1 M U X
Figure 4-3 I/O Port and I/O Control Register for Port 5 Circuit
NOTE Pull-down is not shown in the figure.
16 *
Product Specification (V1.0) 03.10.2006
(This specification is subject to change without further notice)
EM78P159N 8-Bit Microcontroller with OTP ROM
PCRD
Q _ Q
P RD CLK C L
PCW R
P 6 0 /I N T PORT B it 6 o f I O C E D P R CLK C L Q _ Q 0 1 M U X PDRD Q _ Q P RD CLK C L PDW R
IO D
T 10
D
P R
Q _ Q
CLK C L IN T
Figure 4-4a I/O Port and I/O Control Register for P60 (/INT) Circuit
NOTE Pull-high (down) and Open-drain are not shown in the figure.
PCRD
Q _ Q
P RD CLK C L
PCWR
P61~P67 PORT
Q _ Q 0 1
P RD CLK C L
IOD PDWR
M U X TIN PDRD
D
P R CLK C L
Q _ Q
Figure 4-4b I/O Port and I/O Control Register for P61~P67 Circuit
NOTE Pull-high (down) and Open-drain are not shown in the figure.
Product Specification (V1.0) 03.10.2006
(This specification is subject to change without further notice)
* 17
EM78P159N 8-Bit Microcontrollerwith OTP ROM
IOCE.1
D
P R
Q Interrupt RE.1 ENI Instruction
CLK
_ CQ L
T10 T11
P DRQ
CLK
_ CQ L
P QRD
CLK
_ QC L
T17
DISI Instruction Interrupt (Wake-up from SLEEP)
/SLEP
Next Instruction (Wake-up from SLEEP)
Figure 4-4c I/O Port 6 with Input Change Interrupt/Wake-up Block Diagram
4.4.1 Usage of Port 6 Input Change Wake-up/Interrupt Function
Usage of Port 6 Input Status Changed Wake-up/Interrupt (I) Wake-up (a) Before SLEEP 1. Disable WDT 2. Read I/O Port 6 (MOV R6,R6) 3. Execute "ENI" or "DISI" 4. Enable wake-up bit (Set RE ICWE =1) 5. Execute "SLEP" instruction (b) After wake-up Next instruction (II) Wake-up and interrupt (a) Before SLEEP 1. Disable WDT 2. Read I/O Port 6 (MOV R6,R6) 3. Execute "ENI" or "DISI" 4. Enable wake-up bit (Set RE ICWE =1) 5. Enable interrupt (Set IOCF ICIE =1) 6. Execute "SLEP" instruction (b) After wake-up 1. IF "ENI" Interrupt vector (008H) 2. IF "DISI" Next instruction (III) Interrupt (a) Before Port 6 pin change 1. Read I/O Port 6 (MOV R6,R6) 2. Execute "ENI" or "DISI" 3. Enable interrupt (Set IOCF0 ICIE =1) (b) After Port 6 pin changed (interrupt) 1. IF "ENI" Interrupt vector (008H) 2. IF "DISI" Next instruction
18 *
Product Specification (V1.0) 03.10.2006
(This specification is subject to change without further notice)
EM78P159N 8-Bit Microcontroller with OTP ROM
PCRD
VCC
ROC
Q Weakly Pull-up Q
P R C L
D CLK PCWR
PORT
Q
P R C L
D PDWR
IOD
Q
PDRD 0
Rex*
1
M U X
*The Rex is 430K ohm external resistor
Figure 4-5 I/O Port with R-option (P50,P51) Circuit
4.5 RESET and Wake-up
4.5.1 RESET
A RESET is initiated by one of the following events1) Power on reset. 2) /RESET pin input "low," or 3) WDT time-out (if enabled). The device is kept under RESET condition for a period of approximately 18ms2 (one oscillator start-up timer period) after a reset is detected. And if the /Reset pin goes "low" or WDT time-out is active, a reset is generated. Once a RESET occurs, the following functions are performed: The oscillator is running, or will be started. The Program Counter (R2) is set to all "0." All I/O port pins are configured as input mode (high-impedance state).
2
Vdd = 5V, set up time period = 16.8ms 30% Vdd = 3V, set up time period = 18ms 30% Product Specification (V1.0) 03.10.2006
(This specification is subject to change without further notice)
* 19
EM78P159N 8-Bit Microcontrollerwith OTP ROM
The Watchdog timer and prescaler are cleared. When power is switched on, the upper 3 bits of R3 are cleared. The bits of the CONT register are set to all "1" except for the Bit 6 (INT flag). The bits of the IOCA register are set to all "1." The bits of the IOCB register are set to all "1." The IOCC register is cleared. The bits of the IOCD register are set to all "1." Bit 7 of the IOCE register is set to "1," and Bits 4 and 6 are cleared. Bits 0 ~ 2 of RF and Bits 0 ~ 2 of IOCF registers are cleared. The Sleep (power down) mode is asserted by executing the "SLEP" instruction. While entering Sleep mode, WDT (if enabled) is cleared but keeps on running. The controller can be awakened by1) External reset input on /RESET pin, 2) WDT time-out (if enabled), or 3) Port 6 input status change (if enabled). The first two cases will cause the EM78P159N to reset. The T and P flags of R3 are used to determine the source of the reset (wake-up). The last case is considered the continuation of program execution and the global interrupt ("ENI" or "DISI" being executed) decides whether or not the controller branches to the interrupt vector following wake-up. If ENI is executed before SLEP, the instruction will begin to execute from the address 008H after wake-up. If DISI is executed before SLEP, the operation will restart from the succeeding instruction right next to SLEP after wake-up. Wake-up time is dependent on oscillator mode. Under RC mode, the reset time is 32 clocks, and in High XTAL mode, reset time is 2ms and 32clocks. In Low XTAL mode, the reset time is 500ms. The above is applicable only for stable oscillator. Only one of Cases 2 and 3 can be enabled before going into the Sleep mode. That is, [a] if Port 6 Input Status Change Interrupt is enabled before SLEP, WDT must be disabled by software. However, the WDT bit in the option register remains enabled. Hence, the EM78P159N can be awakened only by Case 1 or 3. [b] if WDT is enabled before SLEP, Port 6 Input Status Change Interrupt must be disabled. Hence, the EM78P159N can be awakened only by Case 1 or 2. Refer to the Section 4.6, Interrupt for further details.
20 *
Product Specification (V1.0) 03.10.2006
(This specification is subject to change without further notice)
EM78P159N 8-Bit Microcontroller with OTP ROM
If Port 6 Input Status Change Interrupt is used to wake-up the EM78P159N (Case [a] above), the following instructions must be executed before SLEP: MOV A, @xx000110b CONTW CLR R1 MOV A, @xxxx1110b CONTW WDTC MOV A, @0xxxxxxxb IOW RE MOV R6, R6 BS RE,1 MOV A, @00000x1xb IOW RF ENI (or DISI) SLEP NOP ; Enable (or disable) global interrupt ;Sleep ; Read Port 6 ; Enable wake up control bit ; Enable Port 6 input change interrupt ; Clear WDT and prescaler ;Disable WDT ; Clear TCC and prescaler ; Select WDT prescaler ; Select internal TCC clock
Product Specification (V1.0) 03.10.2006
(This specification is subject to change without further notice)
* 21
EM78P159N 8-Bit Microcontrollerwith OTP ROM
4.5.2 The Summary of the Initialized Values for Registers
Address Name Reset Type Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit 7 X U U U C67 1 1 P X 1 1 P U P P 0 0 P 0 0 Bit 6 C56 1 1 P C66 1 1 P /INT 0 0 P U P P 0 0 P 0 0 Bit 5 C55 1 1 P C65 1 1 P TS 1 1 P U P P 0 0 P 0 0 Bit 4 C54 1 1 P C64 1 1 P TE 1 1 P U P P 0 0 P 0 0 Bit 3 C53 1 1 P C63 1 1 P Bit 2 C52 1 1 P C62 1 1 P Bit 1 C51 1 1 P C61 1 1 P Bit 0 C50 1 1 P C60 1 1 P
N/A
IOC5
N/A
IOC6
N/A
CONT
PSRE PSR2 PSR1 PSR0 1 1 1 1 1 1 1 1 P U P P 0 0 P 0 0 P U P P 0 0 P 0 0 P U P P 0 0 P 0 0 P U P P 0 0 P 0 0
0x00
R0(IAR)
0x01
R1(TCC)
0x02
R2(PC)
*0/P
GP2 0 0 P 1 1 1 X 0 0 0 P67 U P P
*0/P
GP1 0 0 P 1 1 1 P56 U P P P66 U P P
*0/P
GP0 0 0 P U P P P55 U P P P65 U P P
*0/P
T 1
*1/P
P 1
*0/P
Z U P P U P P P52 U P P P62 U P P
*0/P
DC U P P U P P P51 U P P P61 U P P
*0/P
C U P P U P P P50 U P P P60 U P P
0x03
R3(SR)
** **
U P P P54 U P P P64 U P P
** **
U P P P53 U P P P63 U P P
0x04
R4(RSR)
0x05
P5
0x06
P6
22 *
Product Specification (V1.0) 03.10.2006
(This specification is subject to change without further notice)
EM78P159N 8-Bit Microcontroller with OTP ROM Address Name Reset Type Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit Name Power-On /RESET and WDT Wake-Up from Pin Change Bit 7 X U U U X U U U 1 1 P /PD7 1 1 P OD7 0 0 P /PH7 1 1 P WDTE 1 1 1 X U U U U P P Bit 6 X U U U X U U U 1 1 P /PD6 1 1 P OD6 0 0 P /PH6 1 1 P EIS 0 0 P X U U U U P P Bit 5 X U U U X U U U 1 1 P /PD5 1 1 P OD5 0 0 P /PH5 1 1 P X U U U X U U U U P P Bit 4 X U U U X U U U 1 1 P /PD4 1 1 P OD4 0 0 P /PH4 1 1 P Bit 3 X U U U X U U U 1 1 P /PD3 1 1 P OD3 0 0 P /PH3 1 1 P Bit 2 X U U U EXIF 0 0 P 1 1 P /PD2 1 1 P OD2 0 0 P /PH2 1 1 P Bit 1 ICWE 0 0 P ICIF 0 0 P 1 1 P /PD1 1 1 P OD1 0 0 P /PH1 1 1 P Bit 0 X U U U TCIF 0 0 P 1 1 P /PD0 1 1 P OD0 0 0 P /PH0 1 1 P
0x0E
RE(WUE)
0x0F
RF(ISR)
0x0A
IOCA
0x0B
IOCB
0x0C
IOCC
0x0D
IOCD
0x0E
IOCE
ROC PSWE PSW2 PSW1 PSW0 0 0 0 0 0 0 0 0 0 0 P X U U U U P P P X U U U U P P P EXIE 0 0 P U P P P ICIE 0 0 P U P P P TCIE 0 0 P U P P
0x0F
IOCF
0x10~0x2F R10~R2F
* Jump to address 0x08, or execute the instruction next to the "SLEP" instruction. ** Refer to tables provided under next section (Section 4.5.3).
Legend: X: Not used U: Unknown or don't care P: Previous value before reset
Product Specification (V1.0) 03.10.2006
(This specification is subject to change without further notice)
* 23
EM78P159N 8-Bit Microcontrollerwith OTP ROM
4.5.3 The Status of RST, T, and P of STATUS Register
A RESET condition is initiated by the following events 1) A power-on condition, 2) A high-low-high pulse on /RESET pin, and 3) Watchdog timer time-out. The values of T and P listed in the table below are used to check how the processor wakes up. The Values of RST, T, and P after RESET
Reset Type Power on /RESET during Operating mode /RESET wake-up during SLEEP mode WDT during Operating mode WDT wake-up during SLEEP mode Wake-Up on pin change during SLEEP mode T 1 P 1
*P
1 0 0 1
*P
0
*P
0 0
* P: Previous status before reset
The following table shows the events that may affect the status of T and P. The Status of T and P Being Affected by Events
Event Power on WDTC instruction WDT time-out SLEP instruction Wake-Up on pin change during SLEEP mode T 1 1 0 1 1 P 1 1
*P
0 0
* P: Previous status before reset
VDD
Oscillator
D CLK CLR
Q
CLK
Power-on Reset
Voltage Detector
WDTE
WDT
WDT Timeout
Setup Time
RESET
/RESET
Figure 4-6 Controller Reset Block Diagram 24 * Product Specification (V1.0) 03.10.2006
(This specification is subject to change without further notice)
EM78P159N 8-Bit Microcontroller with OTP ROM
4.6 Interrupt
The EM78P159N has three falling-edge interrupts as listed herewith: 1) TCC overflow interrupt 2) Port 6 Input Status Change Interrupt 3) External interrupt [(P60, /INT) pin]. Before the Port 6 Input Status Change Interrupt is enabled, reading Port 6 (e.g., "MOV R6,R6") is necessary. Each Port 6 pin will have this feature if its status changes. Any pin configured as output or P60 pin configured as /INT is excluded from this function. The Port 6 Input Status Changed Interrupt can wake up the EM78P159N from Sleep mode if Port 6 is enabled prior to going into the Sleep mode by executing SLEP. When the chip wakes-up, the controller will continue to execute the succeeding address if the global interrupt is disabled or it will branch into the interrupt vector 008H if the global interrupt is enabled. RF is the interrupt status register that records the interrupt requests in the relative flags/bits. IOCF is an interrupt mask register. The global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction. When one of the interrupts (enabled) occurs, the next instruction will be fetched from address 008H. Once in the interrupt service routine, the source of an interrupt can be determined by polling the flag bits in RF. The interrupt flag bit must be cleared by instructions before leaving the interrupt service routine and before interrupts are enabled to avoid recursive interrupts. The flag (except ICIF bit) in the Interrupt Status Register (RF) is set regardless of the status of its mask bit or the execution of ENI. Note that the outcome of RF will be the logic AND of RF and IOCF (refer to figure below). The RETI instruction ends the interrupt routine and enables the global interrupt (the execution of ENI). When an interrupt is generated by the INT instruction (enabled), the next instruction will be fetched from Address 001H.
VCC
D /IR Q n CLK
P R C L
Q _ Q RFRD
IR Q n IN T IR Q m E N I/D IS I
RF
Q _ Q
P R C L
D CLK IO C F W R
IO D
IO C F /R E S E T
IO C F R D
RFW R
Figure 4-7 Interrupt Input Circuit
Product Specification (V1.0) 03.10.2006
(This specification is subject to change without further notice)
* 25
EM78P159N 8-Bit Microcontrollerwith OTP ROM
4.7 Oscillator
4.7.1 Oscillator Modes
The EM78P159N can be operated in four different oscillator modes, such as External RC oscillator mode (ERC), Internal RC oscillator mode(IRC), High XTAL oscillator mode (HXT), and Low XTAL oscillator mode (LXT). The desired mode can be selected through programming of OSC2, OSC1, and OSC0 in the CODE option register. Table below explains how these 4 oscillator modes are defined with OSC2, OSC1, and OSC0. Oscillator Modes Defined by OSC
Mode ERC (External RC oscillator mode); P55/OSCO act P55 ERC (External RC oscillator mode); P55/OSCO act OSCO IRC (Internal RC oscillator mode) ; P55/OSCO act P55 IRC (Internal RC oscillator mode); P55/OSCO act OSCO MCIRC (Manual calibration IRC mode); P55/OSCO act P55 MCIRC (Manual calibration IRC mode); P55/OSCO act OSCO LXT (Low XTAL oscillator mode) HXT (High XTAL oscillator mode) (default) With Simulator only OSC2 OSC1 OSC0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
NOTE The transient point of system frequency between HXT and LXY is around 400 KHz.
The maximum operational frequency of crystal/resonator under different VDDs is as listed below. Summary of Maximum Operating Speeds
Conditions VDD 2.1 Two cycles with two clocks 3.0 5.0 Max Freq. (MHz) 4.0 8.0 20.0
26 *
Product Specification (V1.0) 03.10.2006
(This specification is subject to change without further notice)
EM78P159N 8-Bit Microcontroller with OTP ROM
4.7.2 Crystal Oscillator/Ceramic Resonators (XTAL)
EM78P159N can be driven by an external clock signal through the OSCI pin as shown in the following figure.
OSCI OSCO EM78P159N
Ext. Clock
Figure 4-8a External Clock Input Circuit
In the most applications, Pin OSCI and Pin OSCO can be connected with a crystal or ceramic resonator to generate oscillation. Figure below depicts such circuit. The same thing applies whether it is in the HXT mode or in the LXT mode. The following table provides the recommended values of C1 and C2. Since each resonator has its own attribute, you should refer to its specification for appropriate values of C1 and C2. RS, a serial resistor, may be necessary for AT strip cut crystal or low frequency mode.
C1 OSCI EM78P159N OSCO RS C2 XTAL
Figure 4-8b Crystal/Resonator Circuit
Capacitor Selection Guide for Crystal Oscillator or Ceramic Resonator
Oscillator Type Ceramic Resonators Frequency Mode HXT Frequency 455 kHz 2.0 MHz 4.0 MHz 32.768kHz 100KHz 200KHz 455KHz 1.0MHz 2.0MHz 4.0MHz C1(pF) 100~150 20~40 10~30 25 25 25 20~40 15~30 15 15 C2(pF) 100~150 20~40 10~30 15 25 25 20~150 15~30 15 15
LXT Crystal Oscillator HXT
Product Specification (V1.0) 03.10.2006
(This specification is subject to change without further notice)
* 27
EM78P159N 8-Bit Microcontrollerwith OTP ROM
NOTE The values of capacitors C1 & C2 are for reference only.
4.7.3 External RC Oscillator Mode
For some applications that do not need a very precise timing calculation, the RC oscillator (Figure 4-9 below) offers a lot of cost savings. Nevertheless, it should be noted that the frequency of the RC oscillator is influenced by the supply voltage, the values of the resistor (Rext), the capacitor (Cext), and even by the operation temperature. Moreover, the frequency also changes slightly from one chip to another due to the manufacturing process variation. In order to maintain a stable system frequency, the values of the Cext should not be less than 20pF, and that the value of Rext should not be greater than 1 M. If they cannot be kept in this range, the frequency can be easily affected by noise, humidity, and leakage. The smaller the Rext in the RC oscillator is, the faster its frequency will be. On the contrary, for very low Rext values, for instance, 1 K, the oscillator becomes unstable because the NMOS cannot discharge the current of the capacitance correctly. Based on the above reasons, it must be kept in mind that all of the supply voltage, the operation temperature, the components of the RC oscillator, the package types, the way the PCB is layout, will affect the system frequency.
Vcc Rext
OSCI Cext EM78P159N
Figure 4-9 External RC Oscillator Mode Circuit
28 *
Product Specification (V1.0) 03.10.2006
(This specification is subject to change without further notice)
EM78P159N 8-Bit Microcontroller with OTP ROM
RC Oscillator Frequencies
Cext Rext 3.3k 20 pF 5.1k 10k 100k 3.3k 100 pF 5.1k 10k 100k 3.3k 300 pF 5.1k 10k 100k Average Fosc 5V, 25C 3.92 MHz 2.67 MHz 1.39MHz 149 kHz 1.39 MHz 940 kHz 480 kHz 52 kHz 595 kHz 400 kHz 200 kHz 21 kHz Average Fosc 3V, 25C 3.65 MHz 2.60 MHz 1.40 MHz 156 kHz 1.33 MHz 920 kHz 475 kHz 50 kHz 560 kHz 390 kHz 200 kHz 20 kHz
NOTE 1. Measured on DIP packages. 2. The values are for design reference only. 3. The frequency drift is about 30%
4.7.4 Internal RC Oscillator Mode
EM78P159N offers a versatile internal RC mode with default frequency value of 4MHz. The Internal RC oscillator mode has other frequencies (1MHz, 8MHz. & 455kHz) that can be set by CODE OPTION (WORD1), RCM1, and RCM0. All these four main frequencies can be calibrated by programming the OPTION Bits C3 ~ C0. The table below describes a typical instance of the calibration. Internal RC Drift Rate (Ta=25, VDD=3.9V5%, VSS=0V)
Internal RC Frequency 4MHz 8MHz 1MHz 455MHz Drift Rate Temperature (-40 ~ +85) 5% 5% 5% 5% Voltage (2.3V ~ 5.5V) 5% 5% 5% 5% Process 4% 4% 4% 4% Total 14% 14% 14% 14%
The above are theoretical values and are provided for reference only. Actual values may vary depending on actual process.
Product Specification (V1.0) 03.10.2006
(This specification is subject to change without further notice)
* 29
EM78P159N 8-Bit Microcontrollerwith OTP ROM
Calibration Selection for Internal RC Mode
C3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 C2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 C1 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 C0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 Cycle Time (ns) 390.6 365.0 342.5 322.6 304.9 289.0 274.7 261.8 250.0 239.2 229.4 220.3 211.9 204.1 196.7 190.1 Frequency (MHz) 2.56 2.74 2.92 3.1 3.28 3.46 3.64 3.82 4.00 4.18 4.36 4.54 4.72 4.9 5.08 5.26
The above are theoretical values and are provided for reference only. Actual values may vary depending on actual process.
4.8 CODE Option Register
The EM78P159N has a CODE option word that is not a part of the normal program memory. The option bits cannot be accessed during normal program execution. Code Option Register and Customer ID Register Arrangement Distribution:
Word 0 Bit12 ~ Bit0 Word 1 Bit12 ~ Bit0 Word 2 Bit12 ~ Bit0
4.8.1 Code Option Register (Word 0)
WORD 0 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 PR2 Bit 1 PR1 Bit 0 PR0 CLKS0 ENWDTB OSC2 OSC1 OSC0 HLP
Bit 0 ~ Bit 2 (PR0 ~ PR2): Protect bits PR0 ~ PR2 are protect bits. Protect types are as follows:
PR2 0 0 0 0 1 1 1 1 30 * PR1 0 0 1 1 0 0 1 1 PR0 0 1 0 1 0 1 0 1 Protect Enable Enable Enable Enable Enable Enable Enable Disable
Product Specification (V1.0) 03.10.2006
(This specification is subject to change without further notice)
EM78P159N 8-Bit Microcontroller with OTP ROM
Bit 3 (HLP):
Power selection 0 = Low power 1 = High power
Bit 4 ~ Bit 6 (OSC0 ~ OSC2): Oscillator Modes Selection bits
Mode ERC (External RC oscillator mode); P55/OSCO act P55 ERC (External RC oscillator mode); P55/OSCO act OSCO IRC (Internal RC oscillator mode) ; P55/OSCO act P55 IRC (Internal RC oscillator mode); P55/OSCO act OSCO MCIRC (Manual calibration IRC mode); P55/OSCO act P55 MCIRC (Manual calibration IRC mode); P55/OSCO act OSCO LXT (Low XTAL oscillator mode) HXT (High XTAL oscillator mode) (default) With Simulator only OSC2 OSC1 OSC0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
NOTE The transient point of system frequency between HXT and LXY is around 400 KHz.
Bit 7 (ENWDTB): Watchdog timer enable bit. 0 = Enable 1 = Disable Bit 8 (CLKS0): Instruction period option bit
Word 0 4 oscillator time periods (default) 2 oscillator time periods CLK0 1 0
Refer to Section 4.12 Instruction Set for further details. Bit 9 ~ Bit 12: Not used, but need to set to "1" all the time to preclude possible error.
4.8.2 Customer ID Register (Word 1)
WORD 0 Bit12 Bit11 Bit10 RCOUT Bit9 Bit8 Bit7 Bit6 CYES Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 RCM1 RCM0
Bit 0 ~ Bit 1 ( RCM0 ~ RCM1): IRC mode selection bits
RCM 1 1 1 0 0 RCM 0 1 0 1 0
Frequency (MHz)
4 8 1 455kHz
Bit 2 ~ Bit 5:
Not used
* 31
Product Specification (V1.0) 03.10.2006
(This specification is subject to change without further notice)
EM78P159N 8-Bit Microcontrollerwith OTP ROM
Bit 6 (CYES):
Instruction cycle selection bit 0 = one instruction cycle 1 = two instruction cycles (default) Not used
Bit 7 ~ Bit 10:
Bits 11 (RCOUT): System clock output enable bit in IRC or ERC mode 0 = OSCO pin is open drain. 1 = OSCO output system clock Bit 12: Not used
4.8.3 Customer ID Register (Word 2)
WORD 0 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 -
Bit 0 ~ Bit 12: User's ID code
4.9 Power On Considerations
Any microcontroller is not guaranteed to start to operate properly before the power supply stays at its steady state. EM78P159N POR voltage range is 1.7V~1.9V. Under customer application, when power is OFF, Vdd must drop to below 1.2V and remains OFF for 10s before power can be switched ON again. This way, the EM78P159N will reset and operates normally. The extra external reset circuit will work well if Vdd can rise at very fast speed (50 ms or less). However, under most cases where critical applications are involved, extra devices are required to assist in solving the power-up problems.
4.10 External Power On Reset Circuit
The circuit shown in the following figure impleVdd ments an external RC to R produce the reset pulse. /RESET D The pulse width (time EM78P159N constant) should be kept long enough for Vdd to Rin C reached minimum operation voltage. This circuit is used when the power supply has a slow rise Figure 4-10 External Power-Up Reset Circuit time. Because the current leakage from the /RESET pin is about 5A, it is recommended that R should not be greater than 40K. In this way, the /RESET pin voltage is held below 0.2V. The diode (D) acts as a short circuit at the moment of power down. The capacitor C will discharge rapidly and fully. Rin, the current-limited resistor, will prevent high current or ESD (electrostatic discharge) from flowing to pin /RESET.
32 * Product Specification (V1.0) 03.10.2006
(This specification is subject to change without further notice)
EM78P159N 8-Bit Microcontroller with OTP ROM
4.11 Residue-Voltage Protection
When the battery is replaced, device power (Vdd) is cut off but residue-voltage remains. The residue-voltage may trips below minimum Vdd, but not to zero. This condition may cause a poor power-on reset. The following figures illustrate two recommended methods on how to build a residue-voltage protection circuit for EM78P159N.
Vdd 33K EM78P159N /RESET 40K 1N4684 Q1 10K
Vdd
Figure 4-11a Residue Voltage Protection Circuit (1)
Vdd EM78P159N Q1 /RESET 40K R2 R1
Vdd
Figure 4-11b Residue Voltage Protection Circuit (2)
Product Specification (V1.0) 03.10.2006
(This specification is subject to change without further notice)
* 33
EM78P159N 8-Bit Microcontrollerwith OTP ROM
4.12 Instruction Set
Each instruction in the instruction set is a 13-bit word divided into an OP code and one or more operands. Normally, all instructions are executed within one single instruction cycle (one instruction consists of 2 oscillator periods), unless the program counter is changed by instruction "MOV R2,A", "ADD R2,A", or by instructions of arithmetic or logic operation on R2 (e.g., "SUB R2,A", "BS(C) R2,6", "CLR R2", ). In this case, the execution takes two instruction cycles. If for some reasons, the specification of the instruction cycle is not suitable for certain applications, try modifying the instruction as follows: (A) Change one instruction cycle to consist of 4 oscillator periods. (B) "JMP," "CALL," "RET," "RETL," "RETI," or the conditional skip ("JBS," "JBC," "JZ," "JZA," "DJZ," "DJZA") commands which were tested to be true, are executed within two instruction cycles. The instructions that are written to the program counter also take two instruction cycles. Case (A) is selected by the CODE Option bit, called CLK. One instruction cycle consists of two oscillator clocks if CLK is low, and four oscillator clocks if CLK is high. Note that once the 4 oscillator periods within one instruction cycle is selected as in Case (A), the internal clock source to TCC should be CLK=Fosc/4, instead of Fosc/ 2. Moreover, the instruction set has the following features: 1) Every bit of any register can be set, cleared, or tested directly. 2) The I/O register can be regarded as general register. That is, the same instruction can operate on I/O register. The following symbols are used in the following Instruction Set table: R represents a register designator that specifies which one of the registers (including operational registers and general purpose registers) is to be utilized by the instruction. b represents a bit field designator that selects the value for the bit which is located in the register "R", and affects operation. K represents an 8 or 10-bit constant or literal value.
34 *
Product Specification (V1.0) 03.10.2006
(This specification is subject to change without further notice)
EM78P159N 8-Bit Microcontroller with OTP ROM
Instruction Binary
0 0000 0000 0000 0 0000 0000 0001 0 0000 0000 0010 0 0000 0000 0011 0 0000 0000 0100 0 0000 0000 rrrr 0 0000 0001 0000 0 0000 0001 0001 0 0000 0001 0010 0 0000 0001 0011 0 0000 0001 0100 0 0000 0001 rrrr 0 0000 01rr rrrr 0 0000 1000 0000 0 0000 11rr rrrr 0 0001 00rr rrrr 0 0001 01rr rrrr 0 0001 10rr rrrr 0 0001 11rr rrrr 0 0010 00rr rrrr 0 0010 01rr rrrr 0 0010 10rr rrrr 0 0010 11rr rrrr 0 0011 00rr rrrr 0 0011 01rr rrrr 0 0011 10rr rrrr 0 0011 11rr rrrr 0 0100 00rr rrrr 0 0100 01rr rrrr 0 0100 10rr rrrr 0 0100 11rr rrrr 0 0101 00rr rrrr 0 0101 01rr rrrr 0 0101 10rr rrrr 0 0101 11rr rrrr 0 0110 00rr rrrr 0 0110 01rr rrrr
Hex
0000 0001 0002 0003 0004 000r 0010 0011 0012 0013 0014 001r 00rr 0080 00rr 01rr 01rr 01rr 01rr 02rr 02rr 02rr 02rr 03rr 03rr 03rr 03rr 04rr 04rr 04rr 04rr 05rr 05rr 05rr 05rr 06rr 06rr
Mnemonic
NOP DAA CONTW SLEP WDTC IOW R ENI DISI RET RETI CONTR IOR R MOV R,A CLRA CLR R SUB A,R SUB R,A DECA R DEC R OR A,R OR R,A AND A,R AND R,A XOR A,R XOR R,A ADD A,R ADD R,A MOV A,R MOV R,R COMA R COM R INCA R INC R DJZA R DJZ R RRCA R RRC R
Operation
No Operation Decimal Adjust A A CONT 0 WDT, Stop oscillator 0 WDT A IOCR Enable Interrupt Disable Interrupt [Top of Stack] PC [Top of Stack] PC, Enable Interrupt CONT A IOCR A AR 0A 0R R-A A R-A R R-1 A R-1 R ARA ARR A&RA A&RR ARA ARR A+RA A+RR RA RR /R A /R R R+1 A R+1 R R-1 A, skip if zero R-1 R, skip if zero R(n) A(n-1), R(0) C, C A(7) R(n) R(n-1), R(0) C, C R(7)
Status Affected
None C None T,P T,P None None None None None None None None Z Z Z,C,DC Z,C,DC Z Z Z Z Z Z Z Z Z,C,DC Z,C,DC Z Z Z Z Z Z None None C C * 35
Product Specification (V1.0) 03.10.2006
(This specification is subject to change without further notice)
EM78P159N 8-Bit Microcontrollerwith OTP ROM
Instruction Binary
0 0110 10rr rrrr 0 0110 11rr rrrr 0 0111 00rr rrrr 0 0111 01rr rrrr 0 0111 10rr rrrr 0 0111 11rr rrrr 0 100b bbrr rrrr 0 101b bbrr rrrr 0 110b bbrr rrrr 0 111b bbrr rrrr 1 00kk kkkk kkkk 1 01kk kkkk kkkk 1 1000 kkkk kkkk 1 1001 kkkk kkkk 1 1010 kkkk kkkk 1 1011 kkkk kkkk 1 1100 kkkk kkkk 1 1101 kkkk kkkk 1 1110 0000 0001 1 1111 kkkk kkkk
Hex
06rr 06rr 07rr 07rr 07rr 07rr 0xxx 0xxx 0xxx 0xxx 1kkk 1kkk 18kk 19kk 1Akk 1Bkk 1Ckk 1Dkk 1E01 1Fkk
Mnemonic
RLCA R RLC R SWAPA R SWAP R JZA R JZ R BC R,b BS R,b JBC R,b JBS R,b CALL k JMP k MOV A,k OR A,k AND A,k XOR A,k RETL k SUB A,k INT ADD A,k
Operation
R(n) A(n+1), R(7) C, C A(0) R(n) R(n+1), R(7) C, C R(0) R(0-3) A(4-7), R(4-7) A(0-3) R(0-3) R(4-7) R+1 A, skip if zero R+1 R, skip if zero 0 R(b) 1 R(b) if R(b)=0, skip if R(b)=1, skip PC+1 [SP], (Page, k) PC (Page, k) PC kA AkA A&kA AkA k A, [Top of Stack] PC k-A A PC+1 [SP], 001H PC k+A A
Status Affected
C C None None None None None None None None None None None Z Z Z None Z,C,DC None Z,C,DC
Note 1: This instruction is applicable to IOC5~IOC6, IOCB~IOCF only. Note 2: This instruction is not recommended for RF operation. Note 3: This instruction cannot operate under RF.
36 *
Product Specification (V1.0) 03.10.2006
(This specification is subject to change without further notice)
EM78P159N 8-Bit Microcontroller with OTP ROM
4.13 Timing Diagrams
AC Test Input/Output Waveform
VDD-0.5V 0.75VDD
TEST POINTS
0.75VDD 0.25VDD
0.25VDD GND+0.5V
AC Testing : Input is driven at VDD-0.5V for logic "1",and GND+0.5V for logic "0".Timing measurements are made at 0.75VDD for logic "1",and 0.25VDD for logic "0".
RESET Timing (CLK="0")
NOP
Instruction 1 Executed
CLK
/RESET
Tdrh
TCC Input Timing (CLKS="0")
Tins CLK
TCC
Ttcc
Figure 4-12 EM78P159N Timing Diagrams
Product Specification (V1.0) 03.10.2006
(This specification is subject to change without further notice)
* 37
EM78P159N 8-Bit Microcontrollerwith OTP ROM
5
Absolute Maximunm Ratings
EM78P159N
Items Temperature under bias Storage temperature Working voltage Working frequency Input voltage Output voltage -40C to 85C -65C to 150C 2.1 to 5.5V DC to 20MHz* Vss-0.3V to Vdd+0.5V Vss-0.3V to Vdd+0.5V Rating
These parameters are theoretical values and have not been tested.
6
Electrical Characteristics
6.1 DC Electrical Characteristic
(Ta=25 C, VDD=5V5%, VSS=0V)
Symbol FXT ERC IIL VIH1 VIL1 VIHT1 VILT1 VIHX1 VILX1 VIH2 VIL2 VIHT2 VILT2 VIHX2 VILX2 VOH1 VOH1 VOL1 VOL1 IPH IPD Parameter XTAL: VDD to 3V XTAL: VDD to 5V ERC: VDD to 5V Input Leakage Current for input pins Input High Voltage (VDD=5V) Input Low Voltage (VDD=5V) Input High Threshold Voltage (VDD=5V) Input Low Threshold Voltage (VDD=5V) Clock Input High Voltage (VDD=5V) Clock Input Low Voltage (VDD=5V) Input High Voltage (VDD=3V) Input Low Voltage (VDD=3V) Input High Threshold Voltage (VDD=3V) Input Low Threshold Voltage (VDD=3V) Clock Input High Voltage (VDD=3V) Clock Input Low Voltage (VDD=3V) Output High Voltage (Ports 5) Output High Voltage (Ports 6) (Schmitt trigger) Output Low Voltage(Port5) Output Low Voltage (Ports 6) (Schmitt trigger) Pull-high current Pull-down current Condition Two cycle with two clocks Two cycle with two clocks R: 5.1K, C: 100 pF VIN = VDD, VSS Ports 5, 6 (Schmitt trigger) Ports 5, 6 (Schmitt trigger) /RESET, TCC (Schmitt trigger) /RESET, TCC (Schmitt trigger) OSCI (Schmitt trigger) OSCI (Schmitt trigger) Ports 5, 6 (Schmitt trigger) Ports 5, 6 (Schmitt trigger) /RESET, TCC (Schmitt trigger) /RESET, TCC (Schmitt trigger) OSCI (Schmitt trigger) OSCI (Schmitt trigger) IOH = -6 mA IOH = -6 mA IOL = 16.5 mA IOL = 16.5 mA Pull-high active, input pin at VSS Pull-down active, input pin at VDD -50 25 -70 50 0.75Vdd Vdd-0.3 0.75Vdd Vdd-0.3 0.75Vdd Vdd-0.3 0.75Vdd Vdd-0.3 0.75Vdd Vdd-0.3 0.75Vdd Vdd-0.3 4.5 4.5 0.5 0.5 -100 120 Min DC DC F30% 940 Typ Max 8.0 20.0 F30% 1 Vdd+0.3 0.25Vdd Vdd+0.3 0.25Vdd Vdd+0.3 0.25Vdd Vdd+0.3 0.25Vdd Vdd+0.3 0.25Vdd Vdd+0.3 0.25Vdd Unit MHz MHz KHz A V V V V V V V V V V V V V V V V A A
38 *
Product Specification (V1.0) 03.10.2006
(This specification is subject to change without further notice)
EM78P159N 8-Bit Microcontroller with OTP ROM Symbol ISB1 ISB2 Parameter Power down current (VDD=5.0V) Power down current (VDD=5.0V) Operating supply current (VDD=3V) at two cycles/four clocks Operating supply current (VDD=3V) at two cycles/four clocks Operating supply current (VDD=5.0V) at two cycles/two clocks Operating supply current (VDD=5.0V) at two cycles/four clocks Condition All input and I/O pins at VDD, output pin floating, WDT disabled All input and I/O pins at VDD, output pin floating, WDT enabled /RESET= 'High', Fosc=32KHz (Crystal type,CLKS="0"), output pin floating, WDT disabled /RESET= 'High', Fosc=32KHz (Crystal type,CLKS="0"), output pin floating, WDT enabled /RESET= 'High', Fosc=4MHz (Crystal type, CLKS="0"), output pin floating, WDT enabled /RESET= 'High', Fosc=10MHz (Crystal type, CLKS="0"), output pin floating, WDT enabled Min Typ 1 6 Max 2 10 Unit A A
ICC1
20
30
A
ICC2
22
32
A
ICC3
1.7
2.5
mA
ICC4
2.7
3.5
mA
These parameters are theoretical values and have not been tested.
6.2 AC Electrical Characteristic
(Ta=25 C, VDD=5V5%, VSS=0V)
Symbol Dclk Tins Ttcc Tdrh Trst Twdt Tset Thold Tdelay Parameter Input CLK duty cycle Instruction cycle time (CLKS="0") TCC input period Device reset hold time /RESET pulse width Watchdog timer period Input pin setup time Input pin hold time Output pin delay time Cload=20pF Ta = 25C Ta = 25C Crystal type RC type Conditions Min 45 100 500 (Tins+20)/N* 11.8 2000 11.8 16.8 0 20 50 21.8 16.8 21.8 Typ 50 Max 55 DC DC Unit % ns ns ns ms ns ms ns ns ns
* N = selected prescaler ratio.
These parameters are theoretical values and have not been tested. Data in the Minimum, Typical, Maximum ("Min","Typ","Max") columns are based on characterization results at 25. This data is for design reference only and has not been tested.
Product Specification (V1.0) 03.10.2006
(This specification is subject to change without further notice)
* 39
EM78P159N 8-Bit Microcontrollerwith OTP ROM
APPENDIX A Package Types
OTP MCU EM78P159NP EM78P159NM EM78159NAS EM78159NKM Package Type DIP SOP SSOP SSOP Pin Count 18 18 20 20 Package Size 300 mil 300 mil 209 mil 209 mil
B Package Information
18-Lead Plastic Dual in Line (PDIP) -- 300 mil
Figure B-1a EM78P159N 18-Lead PDIP Package Type
40 *
Product Specification (V1.0) 03.10.2006
(This specification is subject to change without further notice)
EM78P159N 8-Bit Microcontroller with OTP ROM
18-Lead Plastic Small Outline (SOP) -- 300 mil
Figure B-1b EM78P159N 18-Lead SOP Package Type
20-Lead Plastic Small Outline (SSOP) -- 209 mil
Figure B-1c EM78P159N 20-Lead SSOP Package Type Product Specification (V1.0) 03.10.2006
(This specification is subject to change without further notice)
* 41
EM78P159N 8-Bit Microcontrollerwith OTP ROM
C Quality Assurance and Reliability
C.1 Reliability Test
Test Category Solderability Test Conditions Solder temperature = 2455C for 5 seconds up to the stopper using a rosin-type flux Step 1: TCT 65C (15mins) ~ 150C (15mins), 10 cycles Step 2: bake 125C, TD(endurance) = 24 hrs. Pre-condition Step 3: soak 30C /60%, TD (endurance) = 192hrs. Step 4: IR flow 3cycles (Pkg thickness 2.5mm or Pkg volume 350mm3--2255C) (Pkg thickness 2.5mm or Pkg volume 350mm3--2405C) Temperature cycle test Pressure cooker test High temperature /high humidity test High-temperature storage life High-temperature operating life Latch-up ESD (HBM) -65C (15mins) ~ 150C (15mins), 200 cycles TA =121C, RH = 100%, pressure = 2atm, TD (endurance) = 96 Hrs. TA=85C , RH=85%, TD (endurance) = 168, 500 Hrs For SMD IC (such as SOP, QFP, SOJ, etc.) Remarks
TA=150C, TD (endurance) = 500, 1000Hrs. TA=125C, VCC = Max. operating voltage, TD (endurance) = 168,500, 1000Hrs. TA=25C, VCC = Max. operating voltage, 150mA/20V TA=25C, 3KV
IP_ND,OP_ND,IO_ND IP_NS,OP_NS,IO_NS IP_PD,OP_PD,IO_PD, IP_PS,OP_PS,IO_PS, VDD-VSS(+), VDD_VSS(-)mode
ESD (MM)
TA=25C, 300V
42 *
Product Specification (V1.0) 03.10.2006
(This specification is subject to change without further notice)
EM78P159N 8-Bit Microcontroller with OTP ROM
C.2 Power-On Reset and Vdd Voltage Drop/Rise Timing Test
Vdd /Reset
Internal POR Tpor Power on Reset Tvd Tvr
Symbol Tpor Tvd* Tvr**
Parameter Power on reset time Vdd Voltage drop time Vdd Voltage rise time
Condition Vdd = 5V, -40 to 85 Vdd = 5V, -40 to 85 Vdd = 5V, -40 to 85
Min. 10.5 -
Typ. 16.8 -
Max. 22 1 1
Unit ms s us
* Tvd is the period of Vdd voltage lower than POR voltage. ** Tvr is the period of Vdd voltage higher than 5.5V.
Figure C-1 EM78P159N Power-On Reset and Vdd Voltage Drop/Rise Timing Test Timing Diagram
C.3 Address Trap Detect
An address trap detect is one of the fail-safe function that detects CPU malfunction caused by noise or the like. If the CPU attempts to fetch an instruction from a part of RAM, an internal recovery circuit will be auto started. Until CPU got the correct function, it will execute the next program.
Product Specification (V1.0) 03.10.2006
(This specification is subject to change without further notice)
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EM78P159N 8-Bit Microcontrollerwith OTP ROM
44 *
Product Specification (V1.0) 03.10.2006
(This specification is subject to change without further notice)

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